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? semiconductor components industries, llc, 2006 july, 2006 ? rev. 2 1 publication order number: NCP1600/d NCP1600 high voltage pfc controller with standby power saving the NCP1600 is an active power factor correction controller that operates as a boost pre ? converter in off ? line power supply applications. NCP1600 is optimized for low to medium power, high ? density power supplies requiring a minimum board area, reduced component count and low power dissipation. two comparators are built into this device to improve standby (power) efficiency. with these two comparators, the pfc controller automatically switches itself in between normal mode and standby mode (skip or off mode) to save power consumption during light load conditions. the NCP1600 can achieve deliver follow ? boost operation that is an innovative mode allowing a drastic size reduction of both the inductor and the power switch. ultimately, the solution system cost is significantly lowered. NCP1600 can also work in a traditional constant output voltage mode and intermediate solutions can be easily implemented. this flexibility makes it ideal to optimally cope with a wide range of applications. features ? lose less high ? voltage startup source ? standard constant output voltage or ?follow ? boost? mode ? pfc skip mode and off mode under light load conditions ? selectable switching frequency clamp ? disable pin to stop pfc operation ? restart delay timer ? brown ? out protection for startup ? feedback loop open detection ? output overvoltage comparator ? switch mode operation: voltage mode ? constant on ? time operation that saves the use of an extra multiplier ? improved regulation block dynamic behavior ? internally trimmed reference current source ? internal leading edge blanking (leb) for noise immunity typical applications ? monitor/tv power supplies ? pc power supplies ? notebook pc adapters ? medium power adapters so ? 16 d suffix case 751b 1 pin connections 16 device package shipping ordering information NCP1600d so ? 16 48 units / rail 1 2 3 4 5 6 7 8 16 15 14 12 11 10 9 (top view ) cs agnd vref rd fb_in mir_out vth stb line nc ct vcc pgnd fc gate 13 vcon NCP1600 awlyww a = assembly location wl = wafer lot y = year ww = work week marking diagram http://onsemi.com
NCP1600 http://onsemi.com 2 figure 1. detailed functional diagram ? + frequency clamp bk1 bk4 1 qr ff1 v ref q2 ? + high 15 v/10 v q3 q4 v ref i ref enable c1 2 5 3 4 q q output_ctrl bk2 timer rs latch 3 1 i ref (205 a) ? 60 mv l.e.b. bk3 ? + c2 output_ctrl nor2 + ? 2 5 ? + ? + 12 ? + ? + 7 6 12 3 output_ctrl + ? i ref current mirror current mirror bk6 11 v i ref gnd bk5 i o i o i o 8 1.17 v on 11 v sw2 on sw1 15 pf 11 v output c7 and1 c6 output i o v ref v reg s r r r uvp ovp c3 c4 ics1 i osc ? ch = 2 * i o * i o * / i ref 2.73 v 0.75 v line vcc gate pgnd fc v con fb_in 13 4 14 9 10 16 11 mir_out stb vth ct cs vref rd agnd output ics2 + ? + ? + ? + ? uvlo v ref i ref q1 z15v th_ stdwn output output output nor1 c5 nt1 or1 NCP1600
NCP1600 http://onsemi.com 3 figure 2. representative application circuit ? + frequency clamp bk1 bk4 1 qr ff1 v ref q2 ? + high 15 v/10 v q3 q4 v ref i ref enable c1 2 5 3 4 q q output_ctrl bk2 timer rs latch 3 1 i ref (205 a) ? 60 mv l.e.b. bk3 ? + c2 output_ctrl nor2 + ? 2 5 ? + ? + 12 ? + ? + 7 6 12 3 output_ctrl + ? i ref current mirror current mirror bk6 11 v i ref gn- d bk5 i o i o i o 8 1.17 v on 11 v sw2 on sw1 15 pf 11 v output c7 and1 c6 output i o v ref v reg s r r r uvp ovp c3 c4 ics1 i osc ? ch = 2 * i o * i o * /i ref 2.73 v 0.75 v line vcc gate pgnd fc v con fb_in 13 4 14 9 10 16 11 mir_out stb v th ct cs vref rd agnd output ics2 + ? + ? + ? uvlo v ref i ref q1 z15v th_ stdwn output output output nor1 c5 nt1 or1 + ? + + 0.1 f + + + 1 2 3 4 u2 df06s 0.22 , 400 v 90~264 vac + + NCP1600 4.7 k universal input
NCP1600 http://onsemi.com 4 pin function descriptions pin symbol description 1 agnd analog ground. 2 v ref output reference voltage 6.5 v. 3 restart delay, rd this pin is a high impedance input and is typically connected to a resistor and capacitor to setup the delay time. after this delay time, the ic will turn off the internal startup fet q1. 4 fb_in this pin is designed to receive a current that is proportional to the pre ? converter output voltage. 5 cs this pin is designed to receive a negative voltage signal proportional to the current flowing through the inductor. this information is generally built using a sense resistor. the zero current detection prevents any restart as long as the pin 5 voltage is below ( ? 60 mv). this pin is also used to perform the peak current limitation. the resistor connected between the pin and the current ? sense ? resistor programs the overcurrent threshold. 6 mir_out the current mirror delivers one current which is the same as the pin 4 (fb_in) input current. this current information is used for disabling the pfc boost pre ? converter during standby, overvoltage and undervoltage conditions. 7 v th this pin divides the reference voltage to design the minimum threshold voltage of pfc output v oltage during standby. 8 stb pfc boost pre ? converter standby pin. the pfc enters standby mode (pfc boost pre ? converter enter both skip mode and off mode) when voltage at this pin falls below 1.17 v. this pin also can be connected to the pwm feedback pin. 9 pgnd power ground. 10 gate the gate drive current capability is suited to drive an igbt or a power mosfet. 11 v cc this pin is the positive supply of the ic. the circuit turns on when v cc becomes higher than 15 v, the operating range after startup being 8.0 v up to 30 v. 12 c t the circuit uses an on ? time control mode. this on ? time is controlled by comparing the c t voltage to the v control voltage. c t is charged by the squared feedback current. 13 v con this pin makes available the regulation block output. the capacitor connected between this pin and ground adjusts the control bandwidth. it is typically set below 20 hz to obtain a nondistorted input current. 14 freq. clamp, fc connecting a resistor and capacitor on this pin to program the maximum switch frequency. 15 nc no connection. 16 line this pin connects directly to the rectified ac line voltage source.
NCP1600 http://onsemi.com 5 maximum ratings rating symbol value unit power supply v oltage (transient), pin 11 to both the agnd pin and pgnd pin v cc 30 v power supply voltage (operating), pin 11 to both the agnd pin and pgnd pin v cc 25 v line voltage, pin 16 to both the agnd pin and pgnd pin v line 500 v power supply voltage on all pins except pin 4, pin 11, pin 16, and pin 10 ? ? 0.3 to +10 v feedback pin voltage, pin 4 to both the agnd pin and pgnd pin v fb_in ? 0.3 to +6.5 v gate pin voltage, pin10 to both the agnd pin and pgnd pin v gate ? 0.3 to 15 v restart diode current i in 5.0 ma gate driver output current, source or sink, pin 10 i gate 1.0 a power dissipation and thermal characteristic d suffix, plastic package case 751b maximum power dissipation @ t a = 70 c thermal resistance, junction ? to ? air p d r ja 550 145 mw c/w operating junction temperature t j 150 c storage temperature range t stg ? 55 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22 ? a114. machine model (mm) 200 v per jedec standard: jesd22 ? a115. 2. latchup current maximum rating: 150 ma per jedec standard: jesd78. 3. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020a.
NCP1600 http://onsemi.com 6 electrical characteristics (v cc = 17 v, for typical values t j = 25 c, for min/max values t j = ? 25 to +125 c) characteristic symbol min typ max unit regulation section regulation high current reference i ref 190 200 205 a ratio (regulation low current reference)/i ref i reg ? l /i reg ? h 0.965 0.977 0.99 ? v control impedance z vcontrol ? 300 ? k feedback pin clamp voltage @ i fb = 100 a feedback pin clamp voltage @ i fb = 200 a v fb ? 100 v fb ? 200 2.0 3.0 2.6 3.5 3.0 4.0 v voltage reference voltage reference (i o = 0 ma) v ref 6.25 6.5 6.75 v line regulation (v cc = 11 v to 25 v) reg line ? 5.0 125 mv load regulation (i o = 0 to 5.0 ma) reg load ? 45 125 mv total output variation over line, load and t emperature v ref 6.25 6.5 6.75 v maximum output current i o 5.0 35 ? ma frequency clamp frequency clamp input threshold v th (fc) 1.9 2.0 2.1 v frequency clamp capacitor reset current (v fc = 0.5 v) i reset 0.5 1.5 4.0 ma frequency clamp disable voltage v dfc 7.0 7.8 8.0 v v cc hysteresis startup threshold (v cc increasing) v th(on) 12.5 15 17 v minimum operating voltage after turn ? on (v cc decreasing) v shutdown 8.0 9.5 10.5 v hysteresis v h ? 5.5 ? v timer minimum off time t off 1.2 1.8 2.7 s current mirror current mirror radio at 200 a input current when 13 k resistor on mir_out pin i out /i in 0.99 1.02 1.07 ? oscillator section maximum oscillator swing vt 1.35 1.44 1.6 v charge current @ i fb = 100 a i charge ? 100 87.5 98 112.5 a charge current @ i fb = 200 a i charge ? 200 350 380 450 a ratio multiplier gain over maximum swing k osc 5600 7050 7600 1/(v,a) average internal oscillator pin capacitance over oscillator maximum swing (c t voltage varying from 0 up to 1.5 v) c int ? 15 ? pf discharge time t disch ? 0.5 1.0 s current sense section zero current detection comparator threshold v zcd ? th ? 95 ? 60 ? 15 mv negative clamp level (i cs ? pin = ? 1.0 ma) c i ? neg ? 0.9 ? 0.7 ? 0.3 v bias current @ vcs = v zcd ? th i b ? cs ? 0.2 ? ? a propagation delay (vcs > v zcd ? th ) to gate drive high t zcd ? 500 ? ns current sense pin internal current source i ocp 225 245 260 a leading edge blanking duration led ? 400 ? ns overvoltage protection propagation delay (vcs < v zcd ? th to gate drive low) t ocp ? 160 ? ns
NCP1600 http://onsemi.com 7 electrical characteristics (v cc = 17 v, for typical values t j = 25 c, for min/max values t j = ? 25 to +125 c) characteristic unit max typ min symbol gate driver output source resistance (c t = 0 v, v gate = 14 v) sink resistance (c t = 2.0 v, v gate = 1.0 v) r oh r ol 4.0 4.0 11 8.1 20 20 output voltage rise time (10% ? 90%) (c l = 1.0 nf) t r ? 14 200 ns output voltage fall time (90% ? 10%) (c l = 1.0 nf) t f ? 14 200 ns output voltage in undervoltage (v cc = 10 v, i sink = 1.0 ma) v o(uv) ? ? 0.25 v overvoltage protection section overvoltage protection threshold (c4 comparator) v c4 2.65 2.73 2.8 v propagation delay (v pin6 > 2.73 v to gate drive low) t ovp ? 500 ? ns undervoltage protection section undervoltage protection threshold (c3 comparator) v c3 0.65 0.75 0.8 v propagation delay (v pin6 < 0.75 v to gate drive low) t uvlo ? 500 ? ns standby section standby threshold (c7 comparator) v c7 1.1 1.17 1.25 v propagation delay (v pin8 < 1.17 v to gate drive low) t ovp ? 500 ? ns thermal shutdown section thermal shutdown threshold t stdwn ? 160 ? c hysteresis t stdwn ? 36 ? c total device line startup current (v cc = 0 v, v line = 50 v) (t a = ? 25 v to +100 c) i su 2.0 12.2 20 ma line operating current (v cc = v th(on) , v line = 50 v) i op ? 10 20 ma v cc dynamic operating current (50 khz, c l = 1.0 nf) v cc static operating current (i o = 0) i cc ? ? 4.9 3.9 8.5 ? ma line pin leakage (v line = 500 v) i line ? 20 80 a
NCP1600 http://onsemi.com 8 typical characteristics (junction t emperature from ? 25 c to 125 c) 6.250 6.350 6.450 6.550 6.650 6.750 ? 25 0 25 50 75 100 125 i ref , regulation high current ( a) figure 3. regulation high current reference vs. junction temperature t j , junction t emperature ( c) i reg ? l / i reg ?? h , ratio (regulation low current reference / i ref ) v fb ? 200 , feedback pin clamp v oltage at i fb = 200 a (v) v fb ? 100 , feedback pin clamp v oltage at i fb = 100 a (v) v ref , voltage reference (v) reg line , voltage reference line regulation (mv) 180 190 200 210 220 230 240 ? 25 0 25 50 75 100 125 figure 4. ratio (regulation low current reference / i ref ) vs. junction temperature t j , junction temperature ( c) 0.8 0.9 1.0 1.1 1.2 1.3 ? 25 0 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ? 25 0 25 50 75 100 125 t j , junction t emperature ( c) figure 5. feedback pin clamp voltage at i fb = 100 a vs. junction temperature 0 1 2 3 4 5 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) figure 6. feedback pin clamp voltage at i fb = 200 a vs. junction temperature t j , junction t emperature ( c) figure 7. voltage reference (i o = 0 ma) vs. junction temperature figure 8. voltage reference line regulation (v cc = 11 v to 25 v ) vs. junction temperature 2 4 6 8 10 12 ? 25 0 25 50 75 100 125 t j , junction temperature ( c)
NCP1600 http://onsemi.com 9 1.900 2.000 2.100 ? 25 0 25 50 75 100 125 figure 9. voltage reference load regulation (i o = 0 to 5 ma) vs. junction temperature figure 10. frequency clamp input threshold vs. junction temperature reg load , voltage reference load regulation (mv) figure 11. frequency clamp capacitor reset current (v fc = 0.5 v) vs. junction temperature figure 12. frequency clamp disable voltage vs. junction temperature i reset , frequency clamp capacitor reset current (ma) v dfc , frequency clamp disable v oltage (v) 0 20 40 60 80 100 ? 25 0 25 50 75 100 125 t j , junction t emperature ( c) t j , junction temperature ( c) 0.0 0.5 1.0 1.5 2.0 2.5 ? 25 0 25 50 75 100 125 v th(fc) , frequency clamp input threshold (v) figure 13. v cc startup threshold vs. junction temperature vth (on) , v cc startup threshold (v) 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 ? 25 0 25 50 75 100 125 figure 14. v cc minimum operating voltage after turn ? on vs. junction temperature v shutdown , v cc minimum operating voltage after turn ? on (v) 0.0 2.0 4.0 6.0 8.0 10.0 ? 25 0 25 50 75 100 125 t j , junction t emperature ( c) t j , junction temperature ( c) 0.0 5.0 10.0 15.0 20.0 25.0 ? 25 0 25 50 75 100 125 t j , junction t emperature ( c) t j , junction temperature ( c)
NCP1600 http://onsemi.com 10 v h , v cc hysteresis (v) figure 15. v cc hysteresis vs. junction temperature figure 16. minimum off time vs. junction temperature figure 17. current mirror ratio vs. junction temperature figure 18. maximum oscillator swing vs. junction temperature t off , minimum off time ( s) i out / i in , current mirror ratio vt, maximum oscillator swing (v) figure 19. charge current at i fb = 100 a vs. junction temperature i charge ? 100 , charge current at i fb = 100 a ( a) figure 20. charge current at i fb = 200 a vs. junction temperature i charge ? 200 , charge current at i fb = 200 a ( a) 2.0 3.0 4.0 5.0 6.0 7.0 8.0 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) 0.8 0.9 1.0 1.1 1.2 1.3 1.4 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) 1.0 1.2 1.4 1.6 1.8 2.0 2.2 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) 80 90 100 110 120 130 140 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) 200 250 300 350 400 450 500 550 600 ? 25 0 25 50 75 100 125 t j , junction temperature ( c)
NCP1600 http://onsemi.com 11 figure 21. ratio multiplier gain over maximum swing vs. junction temperature figure 22. discharge time vs. junction temperature t disch , discharge time (us) k osc , ratio multiplier gain over maximum swing (1/v,a) v zcd ? th , zero current detection comparator threshold voltage (mv) figure 23. zero current detection comparator threshold voltage vs. junction temperature figure 24. negative clamp level voltage vs. junction temperature c i ? neg , negative clamp level voltage (v) ? 25 0 25 50 75 100 125 figure 25. current sense pin internal current source vs. junction temperature figure 26. drive output source resistance vs. junction temperature r oh , drive output source resistance ( ) 4000 4500 5000 5500 6000 6500 7000 7500 8000 ? 25 0 25 50 75 100 125 t j , junction t emperature ( c) 0.0 0.4 0.8 1.2 1.6 2.0 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0.0 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 ? 25 0 25 50 75 100 125 t j , junction t emperature ( c) 0 50 100 150 200 250 300 i ocp , current sense pin internal current source ( a) t j , junction t emperature ( c) 0 5 10 15 20 25 ? 25 0 25 50 75 100 125 t j , junction temperature ( c)
NCP1600 http://onsemi.com 12 figure 27. drive output sink resistance vs. junction temperature figure 28. overvoltage protection threshold voltage vs. junction temperature figure 29. undervoltage protection threshold voltage vs. junction temperature figure 30. standby threshold voltage vs. junction temperature figure 31. line startup current vs. junction temperature figure 32. line operating current vs. junction temperature r ol , drive output sink resistance ( ) v c7 , standby threshold v oltage (v) v c4 , overvoltage protection threshold voltage (v) v c3 , undervoltage protection threshold voltage (v) i su , line startup current (ma) i op , line operating current (ma) 0 5 10 15 20 25 30 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) 0.5 0.6 0.7 0.8 0.9 1.0 ? 25 0 25 50 75 100 125 t j , junction t emperature ( c) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) 0 5 10 15 20 25 30 35 40 ? 25 0 25 50 75 100 125 t j , junction t emperature ( c) 0 5 10 15 20 25 30 35 40 ? 25 0 25 50 75 100 125 t j , junction t emperature ( c)
NCP1600 http://onsemi.com 13 figure 33. line pin leakage (v line = 500 v) vs. junction temperature i line , line pin leakage ( a) figure 34. v cc dynamic operating current at c l = 1.0 nf vs. junction temperature i cc , v cc dynamic operating current at c l = 1 nf (ma) i cc , v cc dynamic operating current at i o = 0 (ma) 0 1 2 3 4 5 6 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) t j , junction temperature ( c) figure 35. v cc dynamic operating current at i o = 0 vs. junction temperature 0 1 2 3 4 5 6 ? 25 0 25 50 75 100 125 0 10 20 30 40 50 60 ? 25 0 25 50 75 100 125 t j , junction t emperature ( c)
NCP1600 http://onsemi.com 14 detailed operating description introduction the need of meeting the requirements of legislation on line current harmonic content, results in an increasing demand for cost effective solutions to comply with the power factor regulations. this data sheet describes a monolithic controller specially designed for this purpose. most off?line appliances use a bridge rectifier associated to a huge bulk capacitor to derive raw dc voltage from the utility ac line. figure 36. t ypical circuit without pfc converter load bulk storage capacitor rectifiers + ac line this technique results in a high harmonic content and in poor power factor ratios. in effect, the simple rectification technique draws power from the mains when the instantaneous ac voltage exceeds the capacitor voltage. this occurs near the line voltage peak and results in a high charge current spike. consequently, a poor power factor (in the range of 0.5?0.7) is generated, resulting in an apparent input power that is much higher than the real power. figure 37. line waveforms without pfc ac line v oltage ac line current rectified dc line sag 0 0 v pk active solutions are the most popular way to meet the legislation requirements. they consist of inserting a pfc pre?regulator between the rectifier ? bridge and the bulk capacitor. this interface is, in fact, a step?up smps that outputs a constant voltage while drawing a sinusoidal current from the line. the NCP1600 was developed to control an active solution with the goal of increasing its robustness while lowering its global cost. operating description the NCP1600 is optimized to just as well drive a free running as a synchronized discontinuous voltage mode converter. it also features valuable protections (overvoltage and undervoltage protection, overcurrent limitation, ...) that make the pfc pre ? regulator very safe and reliable while requiring very few external components. in particular, it is able to safely face any uncontrolled direct charges of the output capacitor from the mains which occur when the output voltage is lower than the input voltage (start?up, overload, ...). in addition to the low count of elements, the circuit can run in an innovative mode named ?follower boost? that permits significant reduction of the size of the pre ? converter inductor and power mosfet. with this technique, the output regulation level is not forced to a constant value, but can vary according to the ac line amplitude and to the output power. the gap between the output voltage and the ac line is then lowered, allowing for pre ? converter inductor and power mosfet size reduction. finally, this method brings significant cost reduction. a description of the functional blocks is given below. figure 38. pfc preconverter converter load rectifiers ac line high frequency bypass capacitor bulk storage capacitor + NCP1600 pfc preconverter
NCP1600 http://onsemi.com 15 regulator section by connecting a resistor between the output voltage to be regulated and the pin 4, a feedback current is obtained. typically, this current is built by connecting a resistor between the output voltage and the pin 4. its value is then given by the following equation: i pin4 v o v pin4 r o where: r o is the feedback resistor, v o is the output voltage, v pin4 is the pin 4 clamp value. the feedback current is compared to the reference current so that the regulation block outputs a signal following the characteristic depicted in figure 39. according to the power and the input voltage, the output voltage regulation level varies between two values (v o ) reg ? l and (v o ) reg ? h corresponding to the i reg ? l and i reg ? h levels. figure 39. regulation characteristic 1.5 v regulation block output i o i reg ? l (97% i ref ) i reg ? h (i ref ) the feedback resistor must be chosen so that the feedback current should equal the internal current source i reg ? h when the output voltage exceeds the chosen upper regulation voltage [(v o ) reg ? h ]. consequently: r o (v o ) reg ? h v pin4 i reg ? h in practice, v pin3 is small compared to (v o ) regh and this equation can be simplified as follows (i reg ? h being also replaced by its typical value 200 a): r o 5 (v o ) reg ? h in k the regulation block output is connected to the pin 13 through a 300 k resistor. the pin 13 voltage (v control ) is compared to the oscillator saw ? tooth for pwm control. an external capacitor must be connected between pin 13 and ground, for external loop compensation. the bandwidth typically set below 20 hz so that the regulation block output should be relatively constant over a given ac line cycle. this integration that results in a constant on?time over the ac line period, prevents the mains frequency output ripple from distorting the ac line current. oscillator section the oscillator consists of three phases: ? charge phase: the oscillator capacitor voltage grows up linearly from its bottom value (ground) until it exceeds v control (regulation block output voltage). at that moment, the pwm latch output gets low and the oscillator discharge sequence is set. ? discharge phase: the oscillator capacitor is abruptly discharged down to its valley value (0 v). ? waiting phase: at the end of the discharge sequence, the oscillator voltage is that maintained in a low state until the pwm latch is set again. figure 40. oscillator output_ctrl sw1 15 pf 11 v + ? ics1 i ref i osc ? ch = 2*i o * i o / i ref + ct 12 the oscillator charge current is dependent on the feedback current (i o ). in effect: i charge 2 i o 2 i ref where: i charge is the oscillator charge current, i o is the feedback current (drawn by pin 4), i ref is the internal reference current (200 a). so, the oscillator charge current is linked to the output voltage level as follows: i charge 2(v o v pin4 ) 2 r o 2 i ref where: v o is the output voltage, r o is the feedback resistor, v pin4 is the pin 4 clamp voltage.
NCP1600 http://onsemi.com 16 in practice, v pin4 that is in the range of 2.5 v, is very small compared to v o . the equation can then be simplified by neglecting v pin4 : i charge 2 v o 2 r o 2 i ref it must be noticed that the oscillator terminal (pin 12) has an internal capacitance (c int ) that varies versus the pin 12 voltage. over the oscillator swing, its average value typically equals 15 pf. the total oscillator capacitor is then the sum of the internal and external capacitors. c pin12 c t c int pwm latch section the NCP1600 operates in voltage mode: the regulation block output v control (pin 13 voltage) is compared to the oscillator saw ? tooth so that the gate drive signal (pin 10) is high until the oscillator ramp exceeds v control . the on?time is then given by the following equation: t on c pin12 v control i charge where: t on is the on?time, c pin12 is the total oscillator capacitor (sum of the internal and external capacitor), i charge is the oscillator charge current (pin 12 current), v control is the pin 13 voltage (regulation block output). consequently, replacing i charge by the expression given in the oscillator section : t on r o 2 i ref c pin12 v control 2 v o 2 one can notice that the on?time depends on v o (pre ? converter output voltage) and that the on?time is maximum when v control is maximum (1.5 v typically). at a given vo, the maximum on?time is then expressed by the following equation: (t on ) max r o 2 i ref c pin12 (v control ) max 2 v o 2 this equation can be simplified replacing: 2 i ref (v control ) max by k osc refer to electrical characteristics, oscillator section . then: (t on ) max c pin12 r o 2 k osc v o 2 this equation shows that the maximum on?time is inversely proportional to the squared output voltage. this property is used for follower boost operation (refer to follower boost section). current sense block the inductor current is converted into a voltage by inserting a ground referenced resistor (r cs ) in series with the input diodes bridge (and the input filtering capacitor). therefore a negative voltage proportional to the inductor current is built: v cs ? (r cs i l ) where: i l is the inductor current, r cs is the current sense resistor, vcs is the measured r cs voltage. the negative signal vcs is applied to the current sense through a resistor r ocp . this pin is internally protected by a negative clamp (?0. 7 v) that prevents substrate injection. as long as the pin 5 voltage is lower than (?60 mv), the current sense comparator resets the pwm latch to force the gate drive signal low state. in that condition, the power mosfet cannot be on. during the on?time, the pin 5 information is used for the overcurrent limitation while it serves the zero current detection during the off time.
NCP1600 http://onsemi.com 17 figure 41. current sensing time v ocp zero current detection ( ? 60 mv) v ocp = r ocp x i ocp switch drive inductor current switch drive cs pin voltage zero current detection the zero current detection function guarantees that the mosfet cannot turn on as long as the inductor current hasn?t reached zero (discontinuous mode). the pin 5 voltage is simply compared to the (?60 mv) threshold so that as long as vcs is lower than this threshold, the circuit gate drive signal is kept in low state. consequently, no po wer mosfet turn on is possible until the inductor current is measured as smaller than (60 mv/r cs ) or, the inductor current nearly equals zero.
NCP1600 http://onsemi.com 18 ocp (overcurrent protection) during the power switch conduction (i.e. when the gate drive pin voltage is high), a current source is applied to pin 5. a voltage drop v ocp is then generated across the resistor r ocp that is connected between the sense resistor and the current sense pin (refer to figure 42). so, instead of vcs, the sum (vcs + v ocp ) is compared to ( ? 60 mv) and the maximum permissible current is the solution of the following equation: ? (r cs i pk(max) ) v ocp ? 60 mv where: i pk(max) is the maximum allowed current, r cs is the sensing resistor. the overcurrent threshold is then: i pk(max) (r ocp i ocp ) (60 10 ? 3) r cs where: r ocp is the resistor connected between the pin and the sensing resistor (r cs ), i ocp is the current supplied by the current sense pin when the gate drive signal is high (power switch conduction phase). i ocp equals 245 a typically. practically, the v ocp offset is high compared to 60 mv and the precedent equation can be simplified. the maximum current is then given by the following equation: i pk(max) r ocp (k ) r cs ( ) 0.245 (ma) consequently, the r ocp resistor can program the ocp level no matter what the r cs value is. this gives great freedom in the choice of r cs . in particular, r cs can be utilized as the inrush resistor. a leading edge blanking (leb) circuit has been implemented. this circuitry disconnects the current sense comparator from pin 5 and disables it during the first 400 ns of the power switch conduction. this prevents the block from reacting on the current spikes that generally occur at power switch turn on. consequently, proper operation does not require any filtering capacitor on pin 5. figure 42. current sense block ff1 q q s r r r 0 0 0 + ? i ocp (245 a) sw2 on ics2 5 cs 11 v l.e.b. output_ctrl bk3 1 ? + c2 ? 60 mv output r cs 90~264 vac + ? df06s 2 3 4 1 u2 r ocp
NCP1600 http://onsemi.com 19 figure 43. overvoltage protection ? + current mirror current mirror bk6 11 v ovp c4 2.73 v fb in 4 + ? output 12 k pfc output voltage i o 6 mir out 1.8 m 0.5 w figure 44. undervoltage detection ? + ? + current mirror current mirror bk6 11 v ovp uvp c4 c3 2.73 v fb in 4 + ? + ? output output 12 k pfc output voltage i o 6 0.75 v mir out 1.8 m 0.5 w ovp (overvoltage protection) referring to figure 43, current mirror output i o is relating to pfc output voltage. the current i o flows into the external resistor and a voltage drop developed across pin 6. this voltage then is compared with the overvoltage protection threshold, v c4 , 2.73 v. when the voltage is higher than the v c4 , the ovp comparator, c4 will be enabled and the pfc gate drive disabled as a result to keep the bulk capacitor voltage below the set level. by selecting the value of the external resistor, the ovp voltage can then be determined. with this feature, the maximum bulk capacitor voltage can be set to value below 400 v so that lower cost bulk capacitor can be used. undervoltage protection and feedback loop open detection referring to figure 44, similarly, the pfc function will be bypassed until the pin 6 voltage exceed 0.75 v. this feature is used to avoid the pfc drawing high current while the line voltage fall below a reasonable level in order to protect the power elements. this protection feature is also applicable for feedback loop open detection. while the feedback resistor is open, no current flows into the fb_in pin (pin 4), hence the voltage across pin 6 will be diminished and the protection will be activated. switching frequency clamp refer to figure 45, the switching frequency clamp. the frequency clamp function can be disabled by pull ing the fc pin voltage higher than frequency clamp threshold. while the frequency clamp function is disabled, the pfc gate drive turn ? on depends on zero ? current ? detection of cs pin. by connecting the rc to the frequency clamp pin, the pfc gate drive turn ? on depends on both the fc pin voltage and the cs pin?s zero ? current ? detection. when the fc pin voltage reaches its threshold, the pfc gate drive turn ? on by the zero ? current ? detection of the cs pin. for best results, the minimum off?time, determined by the values of r and c on the fc pin, should be chosen so that t s(min) = t on + t off(fc) . the output drive is inhibited when the voltage at the frequency clamp input is less than 2.0 v. when the output drive is high, c is discharged through an internal 100 a current source. when the output drive switches low, c7 is charged through r fc . the drive output is inhibited until the voltage across c fc reaches 2.0 v, establishing a minimum off?time where: t off ? (r fc )(c fc ) log ln 1 2 v ref
output section the output stage contains a totem pole optimized to minimize the cross conduction current during high speed operation. the gate drive is kept in a sinking mode whenever the undervoltage lockout is active. the rise and fall times have been controlled to typically equal 14 ns while loaded by 1.0 nf.
NCP1600 http://onsemi.com 20 reference section an internal reference current source (i ref ) is trimmed to be 5% accurate over the temperature range (the typical value is 200 a). i ref is the reference used for the regulation. an internal reference voltage (v ref ) is trimmed to be 3.85% accurate over the temperature range (the typical value is 6.5 v). thermal shutdown internal thermal, circuitry sensing is provided to disable the circuit gate drive and then to prevent it from oscillating, if the junction temperature exceeds 160 c typically. the output stage is again enabled when the temperature drops below 124 c typically (36 c hysteresis). follower boost operation traditional pfc pre ? converters provide the load with a regulated voltage that generally equals 400 v or can change according to the mains type (u.s., european, or universal). in the ?follower boost? operation, the pre ? converter output regulation level is not fixed but varies linearly versus the ac line amplitude at a given input power. this technique aims at reducing the gap between the output and the input voltages to minimize the boost efficiency degradation. follower boost benefits the boost presents two phases: ? the on?time during which the power switch is on. the inductor current grows up linearly according to a slope (v in /l p ), where v in is the instantaneous input voltage and l p the inductor value. ? the off?time during which the power switch is off. the inductor current decreases linearly according to the slope (v o ? v in )/l p , where o o is the output voltage. this sequence that terminates when the current equals zero has a duration that is inversely proportional to the gap between the output and input voltages. consequently, the off?time duration becomes longer in follower boost. figure 45. switch frequency clamp fc pin pfc gate cs pin ? 60 mv zero current detection figure 46. follower boost characteristics traditional output v o (follower boost) load vac
NCP1600 http://onsemi.com 21 consequently, for a given peak inductor current, the longer the off ? time, the smaller power switch duty cycle and then its conduction dissipation. this is the first benefit of this technique: the mosfet on?time losses are reduced. the increase of the off ? time duration also results in a switching frequency reduction (for a given inductor value). given that, in practice, the boost inductor is selected to be big enough to limit the switching frequency down to an acceptable level, one can immediately see the second benefit of the follower boost: it allows the use of smaller, lighter and cheaper inductors compared to traditional systems. finally, this technique utilization brings a drastic system cost reduction by lowering the cost of both the inductor and the power switch. figure 47. off ? time duration increase time i pk i l traditional preconverter v in v in i l v in v in i l the power switch is on the power switch is off v out follower boost preconverter follower boost implementation in the NCP1600, the on?time is controlled differently according to the feedback current level. two areas can be defined: ? when the feedback current is higher than i reg ? l (refer to regulation section), the regulation block output (v control ) is modulated to force the output voltage to a desired value. ? on the other hand, when the feedback current is lower than i reg ? l , the regulation block output and therefore, the on?time, are maximum. as explained in the pwm latch section, the on?time is then inversely proportional to the output voltage square. the follower boost is active in these conditions in which the on?time is simply limited by the output voltage level. note: in this equation, the feedback pin voltage (v pin1 ) is neglected compared to the output voltage (refer to the pwm latch section ). t on (t on ) max c pin12 r o 2 k osc v o 2 where: c pin12 is the total oscillator capacitor (sum of the internal and external capacitors ? c int + c t ), k osc is the ratio (oscillator swing over oscillator gain), v o is the output voltage, r o is the feedback resistor. on the other hand, the boost topology has its own rule that dictates the on?time necessary to deliver the required power: t on 4 l p p in v pk 2 where: v pk is the peak ac line voltage, l p is the inductor value, p in is the input power. combining the two equations, one can obtain the follower boost equation: v o r o 2 c pin12 k osc l p p in v pk consequently, a linear dependency links the output voltage to the ac line amplitude at a given input power.
NCP1600 http://onsemi.com 22 the behavior of the output voltage is depicted in figures 48 and 49. in particular, figure 48 illustrates how the output voltage converges to a stable equilibrium level. first, at a given ac line voltage, the on?time is dictated by the power demand. then, the follower boost characteristic makes correspond one output voltage level to this on?time. combining these two laws, it appears that the power level forces the output voltage. one can notice that the system is fully stable: ? if an output voltage increase makes it move away from its equilibrium value, the on?time will immediately diminish according to the follower boost law. this will result in a delivered power decrease. consequently, the supplied power being too low, the output voltage will decrease back. ? in the same way, if the output voltage decreases, more power will be transferred and then the output voltage will increase back. figure 48. follower boost characteristics the regulation block is active output v oltage input power output v oltage input power on ? time t on t on = k/v o 2 p in vac v o (vac)min (vac)max figure 49. follower boost output voltage vac ll vac vac hl v o regulation block is active (p in )min (p in )max v o = v pk p in non usable area vac mode selection the operation mode is simply selected by adjusting the oscillator capacitor value. as shown in figure 49, the output voltage first has an increasing linear characteristic versus the ac line magnitude and then is clamped down to the regulation value. in the traditional mode, the linear area must be rejected. this is achieved by dimensioning the oscillator capacitor so that the boost can deliver the maximum power while the output voltage equals its regulation level and this, whatever the given input voltage. practically, that means that whatever the power and input voltage conditions are, the follower boost would generate output voltages values higher than the regulation level, if there was no regulation block. in other words, if (v o ) reg ? l is the low output regulation level: (v o ) reg ? l r o 2 c t c in k osc l p (p in ) max v pk consequently, c t ? c int 4 k osc l p (p in ) max (v o ) ? reg ? l 2 r o 2 v pk 2 using i reg ? l (regulation block current reference), this equation can be simplified as follows: c t ? c int 4 k osc l p (p in ) 2 v pk 2 in the follower boost case, the oscillator capacitor must be chosen so that the desired characteristics are obtained. consequently, the simple choice of the oscillator capacitor enables the mode selection. standby operation the pfc boost pre ? converter entering standby mode depends on the stb (standby) pin voltage (pin 8 voltage) which is a high impedance input, and can be directly connected to pwm section?s opto ? coupler output to derive pwm output load information. pfc boost pre ? converter will enter standby mode when the voltage at this pin falls below 1.17 v. while the output of c7 is low, the pfc will stay in normal operation and the and1 gate output will stay low for all the time. when the stb pin voltage falls below the threshold, 1.17 v, the output of c7 will go high and the output of the and1 gate will depend on the output of c6. the current flowing from the current on pin 4 is equal to the fb ? in pin (pin 4) current which is derived from the bulk capacitor voltage at the output. the pfc pre ? converter will be disabled when the voltage at pin 6 is higher than the voltage at pin 7. the minimum pfc output voltage can be set by the pin 7 voltage during standby mode. this voltage can be derived from the v ref (pin 2) by a voltage divider network. during standby operation, the pfc boost pre ? converter will enter skip mode when ac input voltage falls below this pre ? set value. the minimum pfc output voltage and pfc boost pre ? converter will enter off mode when ac input voltage higher than the pre ? set minimum pfc output voltage.
NCP1600 http://onsemi.com 23 package dimensions so ? 16 d suffix case 751b ? 05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a s ituation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP1600/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative the products described herein (NCP1600), may be covered by one or more of the following u.s. patents: 5,073,850; 5,862,045; 6,1 77,782. there may be more patents pending. greenline is a trademark of motorola, inc.

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